Syllabus Application
EE 310
Hardware Description Languages
Faculty
Faculty of Engineering and Natural Sciences
Semester
Spring 2025-2026
Course
EE 310 -
Hardware Description Languages
Time/Place
Time
Week Day
Place
Date
14:40-15:30
Wed
FENS-L065
Feb 16-May 22, 2026
12:40-14:30
Thu
FENS-L065
Feb 16-May 22, 2026
Level of course
Undergraduate
Course Credits
SU Credit:3, ECTS:6, Engineering:6
Prerequisites
CS 303
Corequisites
EE 310L
Course Type
Lecture
Instructor(s) Information
Özcan Öztürk
- Email: ozcan.ozturk@sabanciuniv.edu
Course Information
Catalog Course Description
Introduction to hardware description languages; VHDL fundamentals, behavioral and structural models; syntax and basic rules; design entry; behavioral simulation; logic synthesis and synthesizeable code development; design mapping to standard cells and/or field programmable gate array (FPGA).
Course Learning Outcomes:
| 1. | By the end of this course, students should be able to: Describe hardware description languages (HDL) and Verilog HDL; |
|---|---|
| 2. | Design digital circuits; |
| 3. | Write behavioral models of digital circuits; |
| 4. | Write register transfer level (RTL) models of digital circuits; |
| 5. | Verify behavioral and RTL models; |
| 6. | Describe standard cell libraries and FPGAs; |
| 7. | Synthesize RTL models to standard cell libraries and FPGAs; |
| 8. | Implement RTL models on FPGAs and verify their implementations |
Course Objective
This course teaches designing digital circuits, behavioral and RTL modeling of
digital circuits using Verilog HDL, verifying these models, and synthesizing RTL
models to standard cell libraries and FPGAs. Students gain practical experience
by designing, modeling, implementing and verifying several digital circuits.
digital circuits using Verilog HDL, verifying these models, and synthesizing RTL
models to standard cell libraries and FPGAs. Students gain practical experience
by designing, modeling, implementing and verifying several digital circuits.
Sustainable Development Goals (SDGs) Related to This Course:
| Decent Work and Economic Growth | |
| Industry, Innovation and Infrastructure |
Course Materials
Resources:
Jayaram Bhasker, A Verilog HDL Primer. Star Galaxy Publishing, 2005, 3rd Edition.
Digital Design with Chisel by Martin Schoeberl, 2023 (great book, also available online)
David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture, 2nd ed. Morgan Kaufmann, 2013. (Textbook)
Digital Design with Chisel by Martin Schoeberl, 2023 (great book, also available online)
David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture, 2nd ed. Morgan Kaufmann, 2013. (Textbook)